SCOPS ASIC ADR successfully held on October 5, 2024
SCOPS – 2024, Oct 06
The consortium is pleased to announce that the Architecture Design Review of the SCOPS ASIC was successfully completed on October 5, 2024. Based on the specifications defined in the SRR, this review validates the maturity of the ASIC architecture, the preliminary floorplan, and the power budget. The review also proposed the choice of an organic BGA 81 package.
The detailed specifications of the ASIC, along with the first sub-block specifications, are now available. This significant milestone authorizes the start of preliminary design activities, specifically focusing on schematic entry and the definition of a simulation plan for both the ASIC and its sub-blocks.
- Converter functions:
- Self-synchronization with other converters (masterless)
- Fine PWM timing control capability
- Current and Adaptive Voltage Positioning regulation loops
- Full default function without external programming upon enable signal
- I2C interface for advanced control, can be frozen through one time programmation (OTP)
- Architecture:
