SCOPS ASIC PDR successfully held on December 13, 2024

The consortium is pleased to announce that the Preliminary Design Review of the SCOPS ASIC was successfully completed on December 13, 2024. Concurrently, nearly 64% of the sub-blocks' PDRs have also been closed.

Based on the architecture defined during the ADR, this review validates the maturity of the top-level schematic, simulation plan, floorplan, and power budget, along with confirming the final chip size of 5mm x 6mm. It also confirmed the choice of an organic BGA 81 over-molded package.

Thales Alenia Space in France internal checklist has been successfully completed, and the compliance matrix has been assessed. The team is excited to run the first top-level simulations (integrating transistor level and Verilog-A models) in January 2025.

• Floorplan