PROMISE PLL IP CDR Milestone successfully reached

Promise –  february 01, 2022

ISD announces the completion of the PLL IP.

An associative block that enables the PLL to operate with a reference clock from multiple sources (Crystal Oscillator, digital clock or sine wave) and a CMOS Output buffer that will enrich the existing DARE180XH_IO library are included in the CDR data package. The PLL CDR is successful!


PROMISE eFPGA IP CDR Milestone successfully reached – the first critical enabler for ASSP