PROMISE Pilot Circuit – eFPGA integration successful!

Promise –  april 19, 2021

After successful eFPGA CDR and its data package delivery, the eFPGA embedding an adder function passed its first RTL simulation in PROMISE Pilot Circuit. This first simulation paves the way for the Front-end design activities finalization.


PROMISE eFPGA IP CDR Milestone successfully reached – the first critical enabler for ASSP