PROMISE ADC CDR Milestone successfully reached

ISD announces the completion of the ADC IP. This is 6 multiplexed input (differential or single-ended), low-noise, radiation hardened ADC adequate for sampling signals ranging from DC to 40kHz. The ADC converts the input voltage into a 24-bit word using an SPI – like serial interface. The system architecture is based on a 2nd order, discrete-time (switched capacitor), Sigma-Delta modulator. Sampling rates as high as 230 kSps can be supported with the appropriate combination of the master clock frequency and Over Sampling Ratio value.